On the synthesis of regular VLSI architectures for the 1 - D discretewavelet transform

A methodology for synthesizing parallel computational structures has been applied to the Discrete Wavelet Transform algorithm. It is based on linear space-time mapping with constraint driven localization. The data dependence analysis, localization of global variables, and space-time mapping is presented, as well as one realization of a 3-octave systolic array. The DWT algorithm may not be described by a set of Uniform or AAne Recurrence Equations (UREs, AREs), thus it may not be eeciently mapped onto a regular array. However it is still possible to map the DWT algorithm to a systolic array with local communication links by using rst a non-linear index space transformation. The array derived here has latency of 3M=2, where M is the input sequence length, and similar area requirements as solutions proposed elsewhere. In the general case of an arbitrary number of octaves, linear space-time mapping leads to ineecient arrays with long latency due to problems associated with multiprojection.